i2cslave.c 3.3 KB

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  1. /*
  2. * This file is part of the MicroPython project, http://micropython.org/
  3. *
  4. * The MIT License (MIT)
  5. *
  6. * Copyright (c) 2018 Damien P. George
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice shall be included in
  16. * all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include "i2cslave.h"
  27. #if defined(STM32F4)
  28. void i2c_slave_init_helper(i2c_slave_t *i2c, int addr) {
  29. i2c->CR2 = I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN | 4 << I2C_CR2_FREQ_Pos;
  30. i2c->OAR1 = 1 << 14 | addr << 1;
  31. i2c->OAR2 = 0;
  32. i2c->CR1 = I2C_CR1_ACK | I2C_CR1_PE;
  33. }
  34. void i2c_slave_ev_irq_handler(i2c_slave_t *i2c) {
  35. uint32_t sr1 = i2c->SR1;
  36. if (sr1 & I2C_SR1_ADDR) {
  37. // Address matched
  38. // Read of SR1, SR2 needed to clear ADDR bit
  39. sr1 = i2c->SR1;
  40. uint32_t sr2 = i2c->SR2;
  41. i2c_slave_process_addr_match((sr2 >> I2C_SR2_TRA_Pos) & 1);
  42. }
  43. if (sr1 & I2C_SR1_TXE) {
  44. i2c->DR = i2c_slave_process_tx_byte();
  45. }
  46. if (sr1 & I2C_SR1_RXNE) {
  47. i2c_slave_process_rx_byte(i2c->DR);
  48. }
  49. if (sr1 & I2C_SR1_STOPF) {
  50. // STOPF only set at end of RX mode (in TX mode AF is set on NACK)
  51. // Read of SR1, write CR1 needed to clear STOPF bit
  52. sr1 = i2c->SR1;
  53. i2c->CR1 &= ~I2C_CR1_ACK;
  54. i2c_slave_process_rx_end();
  55. i2c->CR1 |= I2C_CR1_ACK;
  56. }
  57. }
  58. #elif defined(STM32F7)
  59. void i2c_slave_init_helper(i2c_slave_t *i2c, int addr) {
  60. i2c->CR1 = I2C_CR1_STOPIE | I2C_CR1_ADDRIE | I2C_CR1_RXIE | I2C_CR1_TXIE;
  61. i2c->CR2 = 0;
  62. i2c->OAR1 = I2C_OAR1_OA1EN | addr << 1;
  63. i2c->OAR2 = 0;
  64. i2c->CR1 |= I2C_CR1_PE;
  65. }
  66. void i2c_slave_ev_irq_handler(i2c_slave_t *i2c) {
  67. uint32_t isr = i2c->ISR;
  68. if (isr & I2C_ISR_ADDR) {
  69. // Address matched
  70. // Set TXE so that TXDR is flushed and ready for the first byte
  71. i2c->ISR = I2C_ISR_TXE;
  72. i2c->ICR = I2C_ICR_ADDRCF;
  73. i2c_slave_process_addr_match(0);
  74. }
  75. if (isr & I2C_ISR_TXIS) {
  76. i2c->TXDR = i2c_slave_process_tx_byte();
  77. }
  78. if (isr & I2C_ISR_RXNE) {
  79. i2c_slave_process_rx_byte(i2c->RXDR);
  80. }
  81. if (isr & I2C_ISR_STOPF) {
  82. // STOPF only set for STOP condition, not a repeated START
  83. i2c->ICR = I2C_ICR_STOPCF;
  84. i2c->OAR1 &= ~I2C_OAR1_OA1EN;
  85. if (i2c->ISR & I2C_ISR_DIR) {
  86. //i2c_slave_process_tx_end();
  87. } else {
  88. i2c_slave_process_rx_end();
  89. }
  90. i2c->OAR1 |= I2C_OAR1_OA1EN;
  91. }
  92. }
  93. #endif