hw_ints.h 5.6 KB

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  1. //*****************************************************************************
  2. //
  3. // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
  4. //
  5. //
  6. // Redistribution and use in source and binary forms, with or without
  7. // modification, are permitted provided that the following conditions
  8. // are met:
  9. //
  10. // Redistributions of source code must retain the above copyright
  11. // notice, this list of conditions and the following disclaimer.
  12. //
  13. // Redistributions in binary form must reproduce the above copyright
  14. // notice, this list of conditions and the following disclaimer in the
  15. // documentation and/or other materials provided with the
  16. // distribution.
  17. //
  18. // Neither the name of Texas Instruments Incorporated nor the names of
  19. // its contributors may be used to endorse or promote products derived
  20. // from this software without specific prior written permission.
  21. //
  22. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23. // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24. // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25. // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26. // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27. // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28. // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29. // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30. // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32. // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. //
  34. //*****************************************************************************
  35. //*****************************************************************************
  36. //
  37. // hw_ints.h - Macros that define the interrupt assignment on CC3200.
  38. //
  39. //*****************************************************************************
  40. #ifndef __HW_INTS_H__
  41. #define __HW_INTS_H__
  42. //*****************************************************************************
  43. //
  44. // The following are defines for the fault assignments.
  45. //
  46. //*****************************************************************************
  47. #define FAULT_NMI 2 // NMI fault
  48. #define FAULT_HARD 3 // Hard fault
  49. #define FAULT_MPU 4 // MPU fault
  50. #define FAULT_BUS 5 // Bus fault
  51. #define FAULT_USAGE 6 // Usage fault
  52. #define FAULT_SVCALL 11 // SVCall
  53. #define FAULT_DEBUG 12 // Debug monitor
  54. #define FAULT_PENDSV 14 // PendSV
  55. #define FAULT_SYSTICK 15 // System Tick
  56. //*****************************************************************************
  57. //
  58. // The following are defines for the interrupt assignments.
  59. //
  60. //*****************************************************************************
  61. #define INT_GPIOA0 16 // GPIO Port S0
  62. #define INT_GPIOA1 17 // GPIO Port S1
  63. #define INT_GPIOA2 18 // GPIO Port S2
  64. #define INT_GPIOA3 19 // GPIO Port S3
  65. #define INT_UARTA0 21 // UART0 Rx and Tx
  66. #define INT_UARTA1 22 // UART1 Rx and Tx
  67. #define INT_I2CA0 24 // I2C controller
  68. #define INT_ADCCH0 30 // ADC Sequence 0
  69. #define INT_ADCCH1 31 // ADC Sequence 1
  70. #define INT_ADCCH2 32 // ADC Sequence 2
  71. #define INT_ADCCH3 33 // ADC Sequence 3
  72. #define INT_WDT 34 // Watchdog Timer0
  73. #define INT_TIMERA0A 35 // Timer 0 subtimer A
  74. #define INT_TIMERA0B 36 // Timer 0 subtimer B
  75. #define INT_TIMERA1A 37 // Timer 1 subtimer A
  76. #define INT_TIMERA1B 38 // Timer 1 subtimer B
  77. #define INT_TIMERA2A 39 // Timer 2 subtimer A
  78. #define INT_TIMERA2B 40 // Timer 2 subtimer B
  79. #define INT_FLASH 45 // FLASH Control
  80. #define INT_TIMERA3A 51 // Timer 3 subtimer A
  81. #define INT_TIMERA3B 52 // Timer 3 subtimer B
  82. #define INT_UDMA 62 // uDMA controller
  83. #define INT_UDMAERR 63 // uDMA Error
  84. #define INT_SHA 164 // SHA
  85. #define INT_AES 167 // AES
  86. #define INT_DES 169 // DES
  87. #define INT_MMCHS 175 // SDIO
  88. #define INT_I2S 177 // McAPS
  89. #define INT_CAMERA 179 // Camera
  90. #define INT_NWPIC 187 // Interprocessor communication
  91. #define INT_PRCM 188 // Power, Reset and Clock Module
  92. #define INT_SSPI 191 // Shared SPI
  93. #define INT_GSPI 192 // Generic SPI
  94. #define INT_LSPI 193 // Link SPI
  95. //*****************************************************************************
  96. //
  97. // The following are defines for the total number of interrupts.
  98. //
  99. //*****************************************************************************
  100. #define NUM_INTERRUPTS 195 //The above number plus 2?
  101. //*****************************************************************************
  102. //
  103. // The following are defines for the total number of priority levels.
  104. //
  105. //*****************************************************************************
  106. #define NUM_PRIORITY 8
  107. #define NUM_PRIORITY_BITS 3
  108. #endif // __HW_INTS_H__