asm_thumb2_float.rst 2.6 KB

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  1. Floating Point instructions
  2. ==============================
  3. These instructions support the use of the ARM floating point coprocessor
  4. (on platforms such as the Pyboard which are equipped with one). The FPU
  5. has 32 registers known as ``s0-s31`` each of which can hold a single
  6. precision float. Data can be passed between the FPU registers and the
  7. ARM core registers with the ``vmov`` instruction.
  8. Note that MicroPython doesn't support passing floats to
  9. assembler functions, nor can you put a float into ``r0`` and expect a
  10. reasonable result. There are two ways to overcome this. The first is to
  11. use arrays, and the second is to pass and/or return integers and convert
  12. to and from floats in code.
  13. Document conventions
  14. --------------------
  15. Notation: ``Sd, Sm, Sn`` denote FPU registers, ``Rd, Rm, Rn`` denote ARM core
  16. registers. The latter can be any ARM core register although registers
  17. ``R13-R15`` are unlikely to be appropriate in this context.
  18. Arithmetic
  19. ----------
  20. * vadd(Sd, Sn, Sm) ``Sd = Sn + Sm``
  21. * vsub(Sd, Sn, Sm) ``Sd = Sn - Sm``
  22. * vneg(Sd, Sm) ``Sd = -Sm``
  23. * vmul(Sd, Sn, Sm) ``Sd = Sn * Sm``
  24. * vdiv(Sd, Sn, Sm) ``Sd = Sn / Sm``
  25. * vsqrt(Sd, Sm) ``Sd = sqrt(Sm)``
  26. Registers may be identical: ``vmul(S0, S0, S0)`` will execute ``S0 = S0*S0``
  27. Move between ARM core and FPU registers
  28. ---------------------------------------
  29. * vmov(Sd, Rm) ``Sd = Rm``
  30. * vmov(Rd, Sm) ``Rd = Sm``
  31. The FPU has a register known as FPSCR, similar to the ARM core's APSR, which stores condition
  32. codes plus other data. The following instructions provide access to this.
  33. * vmrs(APSR\_nzcv, FPSCR)
  34. Move the floating-point N, Z, C, and V flags to the APSR N, Z, C, and V flags.
  35. This is done after an instruction such as an FPU
  36. comparison to enable the condition codes to be tested by the assembler
  37. code. The following is a more general form of the instruction.
  38. * vmrs(Rd, FPSCR) ``Rd = FPSCR``
  39. Move between FPU register and memory
  40. ------------------------------------
  41. * vldr(Sd, [Rn, offset]) ``Sd = [Rn + offset]``
  42. * vstr(Sd, [Rn, offset]) ``[Rn + offset] = Sd``
  43. Where ``[Rn + offset]`` denotes the memory address obtained by adding Rn to the offset. This
  44. is specified in bytes. Since each float value occupies a 32 bit word, when accessing arrays of
  45. floats the offset must always be a multiple of four bytes.
  46. Data Comparison
  47. ---------------
  48. * vcmp(Sd, Sm)
  49. Compare the values in Sd and Sm and set the FPU N, Z,
  50. C, and V flags. This would normally be followed by ``vmrs(APSR_nzcv, FPSCR)``
  51. to enable the results to be tested.
  52. Convert between integer and float
  53. ---------------------------------
  54. * vcvt\_f32\_s32(Sd, Sm) ``Sd = float(Sm)``
  55. * vcvt\_s32\_f32(Sd, Sm) ``Sd = int(Sm)``