cc_pal.c 14 KB

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  1. //*****************************************************************************
  2. // cc_pal.c
  3. //
  4. // simplelink abstraction file for CC3200
  5. //
  6. // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
  7. //
  8. //
  9. // Redistribution and use in source and binary forms, with or without
  10. // modification, are permitted provided that the following conditions
  11. // are met:
  12. //
  13. // Redistributions of source code must retain the above copyright
  14. // notice, this list of conditions and the following disclaimer.
  15. //
  16. // Redistributions in binary form must reproduce the above copyright
  17. // notice, this list of conditions and the following disclaimer in the
  18. // documentation and/or other materials provided with the
  19. // distribution.
  20. //
  21. // Neither the name of Texas Instruments Incorporated nor the names of
  22. // its contributors may be used to endorse or promote products derived
  23. // from this software without specific prior written permission.
  24. //
  25. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26. // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27. // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28. // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29. // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30. // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31. // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32. // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33. // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34. // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35. // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. //
  37. //*****************************************************************************
  38. //Simplelink includes
  39. #include <simplelink.h>
  40. #include <cc_pal.h>
  41. //Driverlib includes
  42. #include <hw_ints.h>
  43. #include <hw_types.h>
  44. #include <pin.h>
  45. #include <hw_memmap.h>
  46. #include <hw_mcspi.h>
  47. #include <hw_common_reg.h>
  48. #include <rom.h>
  49. #include <rom_map.h>
  50. #include <spi.h>
  51. #include <prcm.h>
  52. #include <rom.h>
  53. #include <rom_map.h>
  54. #include <hw_ints.h>
  55. #include <interrupt.h>
  56. #include <utils.h>
  57. #define REG_INT_MASK_SET 0x400F7088
  58. #define REG_INT_MASK_CLR 0x400F708C
  59. #define APPS_SOFT_RESET_REG 0x4402D000
  60. #define OCP_SHARED_MAC_RESET_REG 0x4402E168
  61. #define SPI_RATE_20M 20000000
  62. #define UNUSED(x) (x = x)
  63. //
  64. // GLOBAL VARIABLES -- Start
  65. //
  66. volatile Fd_t g_SpiFd =0;
  67. P_EVENT_HANDLER g_pHostIntHdl = NULL;
  68. //
  69. // GLOBAL VARIABLES -- End
  70. //
  71. //****************************************************************************
  72. // LOCAL FUNCTION PROTOTYPES
  73. //****************************************************************************
  74. static int spi_Read_CPU(unsigned char *pBuff, int len);
  75. static int spi_Write_CPU(unsigned char *pBuff, int len);
  76. //****************************************************************************
  77. // LOCAL FUNCTION DEFINITIONS
  78. //****************************************************************************
  79. /*!
  80. \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff.
  81. \param pBuff - points to first location to start writing the data
  82. \param len - number of bytes to read from the SPI channel
  83. \return upon successful completion, the function shall return Read Size.
  84. Otherwise, -1 shall be returned
  85. \sa spi_Read_CPU , spi_Write_CPU
  86. \note
  87. \warning
  88. */
  89. int spi_Read_CPU(unsigned char *pBuff, int len)
  90. {
  91. unsigned long ulCnt;
  92. unsigned long ulStatusReg;
  93. unsigned long *ulDataIn;
  94. unsigned long ulTxReg;
  95. unsigned long ulRxReg;
  96. MAP_SPICSEnable(LSPI_BASE);
  97. //
  98. // Initialize local variable.
  99. //
  100. ulDataIn = (unsigned long *)pBuff;
  101. ulCnt = (len + 3) >> 2;
  102. ulStatusReg = LSPI_BASE+MCSPI_O_CH0STAT;
  103. ulTxReg = LSPI_BASE + MCSPI_O_TX0;
  104. ulRxReg = LSPI_BASE + MCSPI_O_RX0;
  105. //
  106. // Reading loop
  107. //
  108. while(ulCnt--)
  109. {
  110. while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_TXS ));
  111. HWREG(ulTxReg) = 0xFFFFFFFF;
  112. while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_RXS ));
  113. *ulDataIn = HWREG(ulRxReg);
  114. ulDataIn++;
  115. }
  116. MAP_SPICSDisable(LSPI_BASE);
  117. return len;
  118. }
  119. /*!
  120. \brief attempts to write up to len bytes to the SPI channel
  121. \param pBuff - points to first location to start getting the data from
  122. \param len - number of bytes to write to the SPI channel
  123. \return upon successful completion, the function shall return write size.
  124. Otherwise, -1 shall be returned
  125. \sa spi_Read_CPU , spi_Write_CPU
  126. \note This function could be implemented as zero copy and return only upon successful completion
  127. of writing the whole buffer, but in cases that memory allocation is not too tight, the
  128. function could copy the data to internal buffer, return back and complete the write in
  129. parallel to other activities as long as the other SPI activities would be blocked untill
  130. the entire buffer write would be completed
  131. \warning
  132. */
  133. int spi_Write_CPU(unsigned char *pBuff, int len)
  134. {
  135. unsigned long ulCnt;
  136. unsigned long ulStatusReg;
  137. unsigned long *ulDataOut;
  138. unsigned long ulDataIn;
  139. unsigned long ulTxReg;
  140. unsigned long ulRxReg;
  141. MAP_SPICSEnable(LSPI_BASE);
  142. //
  143. // Initialize local variable.
  144. //
  145. ulDataOut = (unsigned long *)pBuff;
  146. ulCnt = (len +3 ) >> 2;
  147. ulStatusReg = LSPI_BASE+MCSPI_O_CH0STAT;
  148. ulTxReg = LSPI_BASE + MCSPI_O_TX0;
  149. ulRxReg = LSPI_BASE + MCSPI_O_RX0;
  150. //
  151. // Writing Loop
  152. //
  153. while(ulCnt--)
  154. {
  155. while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_TXS ));
  156. HWREG(ulTxReg) = *ulDataOut;
  157. while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_RXS ));
  158. ulDataIn = HWREG(ulRxReg);
  159. ulDataOut++;
  160. }
  161. MAP_SPICSDisable(LSPI_BASE);
  162. UNUSED(ulDataIn);
  163. return len;
  164. }
  165. /*!
  166. \brief open spi communication port to be used for communicating with a SimpleLink device
  167. Given an interface name and option flags, this function opens the spi communication port
  168. and creates a file descriptor. This file descriptor can be used afterwards to read and
  169. write data from and to this specific spi channel.
  170. The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
  171. set to hardcoded values in this function.
  172. \param ifName - points to the interface name/path. The interface name is an
  173. optional attributes that the simple link driver receives
  174. on opening the device. in systems that the spi channel is
  175. not implemented as part of the os device drivers, this
  176. parameter could be NULL.
  177. \param flags - option flags
  178. \return upon successful completion, the function shall open the spi channel and return
  179. a non-negative integer representing the file descriptor.
  180. Otherwise, -1 shall be returned
  181. \sa spi_Close , spi_Read , spi_Write
  182. \note
  183. \warning
  184. */
  185. Fd_t spi_Open(char *ifName, unsigned long flags)
  186. {
  187. unsigned long ulBase;
  188. unsigned long ulSpiBitRate = SPI_RATE_20M;
  189. //NWP master interface
  190. ulBase = LSPI_BASE;
  191. //Enable MCSPIA2
  192. MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
  193. //Disable Chip Select
  194. MAP_SPICSDisable(ulBase);
  195. //Disable SPI Channel
  196. MAP_SPIDisable(ulBase);
  197. // Reset SPI
  198. MAP_SPIReset(ulBase);
  199. //
  200. // Configure SPI interface
  201. //
  202. MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
  203. ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
  204. (SPI_SW_CTRL_CS |
  205. SPI_4PIN_MODE |
  206. SPI_TURBO_OFF |
  207. SPI_CS_ACTIVEHIGH |
  208. SPI_WL_32));
  209. MAP_SPIEnable(ulBase);
  210. g_SpiFd = 1;
  211. return g_SpiFd;
  212. }
  213. /*!
  214. \brief closes an opened spi communication port
  215. \param fd - file descriptor of an opened SPI channel
  216. \return upon successful completion, the function shall return 0.
  217. Otherwise, -1 shall be returned
  218. \sa spi_Open
  219. \note
  220. \warning
  221. */
  222. int spi_Close(Fd_t fd)
  223. {
  224. unsigned long ulBase = LSPI_BASE;
  225. g_SpiFd = 0;
  226. //Disable Chip Select
  227. MAP_SPICSDisable(LSPI_BASE);
  228. //Disable SPI Channel
  229. MAP_SPIDisable(ulBase);
  230. // Reset SPI
  231. MAP_SPIReset(ulBase);
  232. // Disable SPI Peripheral
  233. MAP_PRCMPeripheralClkDisable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
  234. return 0;
  235. }
  236. /*!
  237. \brief closes an opened spi communication port
  238. \param fd - file descriptor of an opened SPI channel
  239. \return upon successful completion, the function shall return 0.
  240. Otherwise, -1 shall be returned
  241. \sa spi_Open
  242. \note
  243. \warning
  244. */
  245. int spi_Read(Fd_t fd, unsigned char *pBuff, int len)
  246. {
  247. if (fd != 1 || g_SpiFd != 1) {
  248. return -1;
  249. }
  250. return spi_Read_CPU(pBuff, len);
  251. }
  252. /*!
  253. \brief attempts to write up to len bytes to the SPI channel
  254. \param fd - file descriptor of an opened SPI channel
  255. \param pBuff - points to first location to start getting the data from
  256. \param len - number of bytes to write to the SPI channel
  257. \return upon successful completion, the function shall return 0.
  258. Otherwise, -1 shall be returned
  259. \sa spi_Open , spi_Read
  260. \note This function could be implemented as zero copy and return only upon successful completion
  261. of writing the whole buffer, but in cases that memory allocation is not too tight, the
  262. function could copy the data to internal buffer, return back and complete the write in
  263. parallel to other activities as long as the other SPI activities would be blocked untill
  264. the entire buffer write would be completed
  265. \warning
  266. */
  267. int spi_Write(Fd_t fd, unsigned char *pBuff, int len)
  268. {
  269. if (fd != 1 || g_SpiFd != 1) {
  270. return -1;
  271. }
  272. return spi_Write_CPU(pBuff,len);
  273. }
  274. /*!
  275. \brief register an interrupt handler for the host IRQ
  276. \param InterruptHdl - pointer to interrupt handler function
  277. \param pValue - pointer to a memory strcuture that is passed to the interrupt handler.
  278. \return upon successful registration, the function shall return 0.
  279. Otherwise, -1 shall be returned
  280. \sa
  281. \note If there is already registered interrupt handler, the function should overwrite the old handler
  282. with the new one
  283. \warning
  284. */
  285. int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue)
  286. {
  287. if(InterruptHdl == NULL)
  288. {
  289. //De-register Interprocessor communication interrupt between App and NWP
  290. #ifdef SL_PLATFORM_MULTI_THREADED
  291. osi_InterruptDeRegister(INT_NWPIC);
  292. #else
  293. MAP_IntDisable(INT_NWPIC);
  294. MAP_IntUnregister(INT_NWPIC);
  295. MAP_IntPendClear(INT_NWPIC);
  296. #endif
  297. }
  298. else
  299. {
  300. #ifdef SL_PLATFORM_MULTI_THREADED
  301. MAP_IntPendClear(INT_NWPIC);
  302. osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl,INT_PRIORITY_LVL_1);
  303. #else
  304. MAP_IntRegister(INT_NWPIC, InterruptHdl);
  305. MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
  306. MAP_IntPendClear(INT_NWPIC);
  307. MAP_IntEnable(INT_NWPIC);
  308. #endif
  309. }
  310. return 0;
  311. }
  312. /*!
  313. \brief Masks host IRQ
  314. \sa NwpUnMaskInterrupt
  315. \warning
  316. */
  317. void NwpMaskInterrupt()
  318. {
  319. (*(unsigned long *)REG_INT_MASK_SET) = 0x1;
  320. }
  321. /*!
  322. \brief Unmasks host IRQ
  323. \sa NwpMaskInterrupt
  324. \warning
  325. */
  326. void NwpUnMaskInterrupt()
  327. {
  328. (*(unsigned long *)REG_INT_MASK_CLR) = 0x1;
  329. }
  330. #ifdef DEBUG
  331. /*!
  332. \brief Preamble to the enabling the Network Processor.
  333. Placeholder to implement any pre-process operations
  334. before enabling networking operations.
  335. \sa sl_DeviceEnable
  336. \note belongs to \ref ported_sec
  337. */
  338. void NwpPowerOnPreamble(void)
  339. {
  340. #define MAX_RETRY_COUNT 1000
  341. unsigned int sl_stop_ind, apps_int_sts_raw, nwp_lpds_wake_cfg;
  342. unsigned int retry_count;
  343. /* Perform the sl_stop equivalent to ensure network services
  344. are turned off if active */
  345. HWREG(0x400F70B8) = 1; /* APPs to NWP interrupt */
  346. UtilsDelay(800000/5);
  347. retry_count = 0;
  348. nwp_lpds_wake_cfg = HWREG(0x4402D404);
  349. sl_stop_ind = HWREG(0x4402E16C);
  350. if((nwp_lpds_wake_cfg != 0x20) && /* Check for NWP POR condition */
  351. !(sl_stop_ind & 0x2)) /* Check if sl_stop was executed */
  352. {
  353. /* Loop until APPs->NWP interrupt is cleared or timeout */
  354. while(retry_count < MAX_RETRY_COUNT)
  355. {
  356. apps_int_sts_raw = HWREG(0x400F70C0);
  357. if(apps_int_sts_raw & 0x1)
  358. {
  359. UtilsDelay(800000/5);
  360. retry_count++;
  361. }
  362. else
  363. {
  364. break;
  365. }
  366. }
  367. }
  368. HWREG(0x400F70B0) = 1; /* Clear APPs to NWP interrupt */
  369. UtilsDelay(800000/5);
  370. /* Stop the networking services */
  371. NwpPowerOff();
  372. }
  373. #endif
  374. /*!
  375. \brief Enable the Network Processor
  376. \sa sl_DeviceDisable
  377. \note belongs to \ref ported_sec
  378. */
  379. void NwpPowerOn(void)
  380. {
  381. //bring the 1.32 eco out of reset
  382. HWREG(0x4402E16C) &= 0xFFFFFFFD;
  383. //NWP Wakeup
  384. HWREG(0x44025118) = 1;
  385. #ifdef DEBUG
  386. UtilsDelay(8000000);
  387. #endif
  388. //UnMask Host Interrupt
  389. NwpUnMaskInterrupt();
  390. }
  391. /*!
  392. \brief Disable the Network Processor
  393. \sa sl_DeviceEnable
  394. \note belongs to \ref ported_sec
  395. */
  396. void NwpPowerOff(void)
  397. {
  398. //Must delay 300 usec to enable the NWP to finish all sl_stop activities
  399. UtilsDelay(300*80/3);
  400. //Mask Host Interrupt
  401. NwpMaskInterrupt();
  402. //Switch to PFM Mode
  403. HWREG(0x4402F024) &= 0xF7FFFFFF;
  404. //sl_stop eco for PG1.32 devices
  405. HWREG(0x4402E16C) |= 0x2;
  406. UtilsDelay(800000);
  407. }